The present invention relates to an analog synchronization circuit which is provided in a semiconductor memory device, such as a synchronous DRAM, and generates, from an external clock signal, an internal clock signal synchronous with this external clock signal.
This type of semiconductor memory device requires that the internal clock signal generated inside a chip should be synchronized with an external clock signal supplied from outside the chip. When the external clock signal is received at an input buffer in the chip and is distributed inside the chip, the phase of the clock signal inside the chip differs from the phase of the clock signal outside the chip due to delays made by buffers and lines. To avoid this shortcoming, various synchronization circuits which synchronize the internal clock signal with the external clock signal have been developed.
As such synchronization circuits, there are mirror type DLLs (Delay Locked Loops) which include an SMD (Synchronous Mirror Delay) used in, for example, "A 2.5 ns Clock Access 250 MHz 256 Mb SDRAM with a Synchronous Mirror Delay" by T. Saeki, et al., ISSCC Digest of Technical Papers, pp. 374-375, February 1996, and an STBD (Synchronous Traced Backward Delay) described in the U.S. Pat. Nos. 5,867,432, 5,986,949, and 6,034,901. The mirror type DLL has a fast synchronization speed and can generate an internal clock signal synchronous with an external clock signal from the third clock of the external clock signal.
FIG. 1 shows one example of a conventional mirror type DLL. This mirror type DLL comprises an input buffer IB, an output buffer OB, a delay monitor DM which is a replica circuit of those buffers, and a delay line DL. The delay line DL comprises a forward pulse delay line DL1 and a backward pulse delay line DL2, and a analog synchronization operation is carried out by a mirror operation which reflects the delay time on the forward pulse delay line DL1 onto the backward pulse delay line DL2. An important factor in determining the synchronization precision is how to accurately make the delay times on both delay lines equal to each other.
The conventional delay line DL is constituted by connecting a plurality of logic gates, such as inverter circuits, in series. The delay time on the delay line is determined by how many stages of logic gates, which constitute the backward pulse delay line DL2, a backward pulse passes based on information on how many stages of logic gates, which constitute the forward pulse delay line DL1, a forward pulse has passed. Apparently, the delay time becomes a quantized quantity which is the number of stages of logic gates.
As shown in FIG. 2, therefore, the amount of delay on the forward pulse delay line does not become equal to the amount of delay on the backward pulse delay line, thus generating a quantization error.